This application claims the priority benefit of Taiwan application serial no. 91134043, filed on Nov. 22, 2002.
1. Field of Invention
The present invention relates to a method for fabricating thin film transistor array and driving circuit. More particularly, the present invention relates to a method of fabricating thin film transistor array and driving circuit that uses just six masking operations.
2. Description of Related Art
In recent years, the rapid advance in the fabrication of semiconductor devices and display devices has lead to the popularization of multimedia systems. Due to the production of high-quality and low-cost displays such as cathode ray tubes, these displays now represent a large chunk in the display market. However, from the standpoint of a desktop display user or an environmentalist, a cathode ray tube is bulky, consumes a lot of energy and is also a source of radiation. Since a lot of material is required to fabricate each cathode ray tube and a lot of energy is wasted in its operation, other types of displays including thin film transistor liquid crystal display (TFT-LCD) are developed as a substitute. A conventional TFT-LCD is a slim and compact display capable of producing high-quality images. Each TFT-LCD uses very little energy and is virtually radiation-free. All these advantages have championed the TFT-LCD in the mainstream display market.
In general, a thin film transistor may be classified as an amorphous thin film transistor or a polysilicon thin film transistor. A polysilicon thin film transistor fabricated using a low-temperature polysilicon (LTPS) technique is different from an amorphous thin film transistor using an amorphous silicon (a-Si) technique. The LTPS transistor has an electron mobility greater than 200 cm2/V-sec and hence the thin film transistor can have a smaller dimension, a larger aperture ratio and a lower power rating. In addition, the LTPS process also permits the concurrent fabrication of a portion of the driving circuit and the thin film transistor in the same substrate so that the subsequently formed liquid crystal display panel has a greater reliability and a lower average production cost.
FIGS. 1A to 1H are schematic cross-sectional views showing the progression of steps for fabricating a conventional thin film transistor array and driving circuit. As shown in FIG. 1A, a substrate 100 is provided. A polysilicon layer is formed over the substrate 100. Thereafter, the polysilicon layer is patterned using a first masking process (Mask 1) so that a plurality of poly-islands 102a, 102b and 102c are formed over the substrate 100. The poly-island 102a is a location for forming a thin film transistor while the poly-islands 102b and 102c are locations for forming a driving circuit such as a complementary metal-oxide-semiconductor (CMOS) circuit. Since the poly-island 102a is eventually transformed into a thin film transistor, poly-islands 102a are normally positioned on top of the substrate 100 as an array. Similarly, since the poly-islands 102b and 102c are eventually transformed into driving circuits, the poly-islands 102b and 102c are normally positioned close to the peripheral region of the substrate 100.
As shown in FIG. 1B, a first dielectric layer 104 and a conductive layer (not shown) are sequentially formed over the substrate 100 with the poly-islands 102a, 102b and 102c thereon. The conductive layer is patterned using a second masking process (Mask 2) to form gates 106a, 106b and 106c over the poly-islands 102a, 102b and 102c respectively and the lower electrode 108 of a storage capacity on a suitable location on the substrate 100.
As shown in FIG. 1C, N+ doped regions 110 and N+ doped regions 112 are patterned out inside the island 102a and the island 102c using a third masking process (Mask 3). The N+ doped regions 110 inside the island 102a is located on each side of the gate 106a and the N+ doped regions 112 inside the island 102c are located on each side of the gate 106c. 
As shown in FIG. 1D, Nxe2x88x92 doped regions 114 are patterned inside the island 102a and Nxe2x88x92 doped regions 116 are patterned inside the island 102c using a fourth masking process (Mask 4). Each Nxe2x88x92 doped region 114 inside the island 102a is located between the gate 106a and one N+ doped regions 110. Similarly, each Nxe2x88x92 doped region 116 inside the island 102c is located between the gate 106c and one N+ doped region 112.
As shown in FIG. 1E, P+ doped regions 118 are patterned inside the island 102b using a fifth masking process (Mask 5). The P+ doped regions 118 inside the island 102b are located on each side of the gate 106b. 
As shown in FIG. 1F, a second dielectric layer 120 is formed over the substrate 100. Thereafter, the first dielectric layer 104 and the second dielectric layer 120 are patterned using a sixth masking process (Mask 6) to form openings 122a, 122b and 122c. The opening 122a exposes the N+ doped region 110, the opening 122b exposes the P+ doped region 118 and the opening 122c exposes the N+ doped region 112.
As shown in FIG. 1G, a conductive layer (not shown) is formed over the second dielectric layer 120. Thereafter, the conductive layer is patterned using a seventh masking process (Mask 7) to form source/drain terminals 124 (comprising 124a, 124b and 124c respectively). The source/drain terminals 124 are electrically connected to the N+ doped region 110, the P+ doped region 118 and the N+ doped region 112 through the opening 122a, the opening 122b and the opening 122c respectively.
As shown in FIG. 1H, a planarization layer 126 is formed over the substrate 100 with the source/drain terminals 124 thereon. Thereafter, the planarization layer 126 is patterned using an eighth masking process (Mask 8) to form an opening 128 for exposing the source/drain terminal 124a. After patterning the planarization layer 126, a conductive layer (not shown) is formed over the substrate 100. The conductive layer is a transparent layer typically made from indium-tin-oxide material. The conductive layer is patterned using a ninth masking process (Mask 9) to form a pixel electrode 130.
As shown on the left side of FIG. 1H, the Nxe2x88x92 doped region 116 and the N+ doped region 112 inside the island 102c, the gate 106c and the source/drain terminal 124c together constitute an Nxe2x88x92 type metal-oxide-semiconductor (NMOS) transistor. The P+ doped region 118 inside the island 102b, the gate 106b and the source/drain terminal 124b together constitute a P-type metal-oxide-semiconductor (PMOS) transistor. The NMOS transistor and the PMOS transistor together constitute a complementary metal-oxide-semiconductor (CMOS) transistor. The CMOS transistor on the substrate 100 is a driving circuit for driving the thin film transistor on the right side of FIG. 1H and hence controlling pixel display.
As shown on the right side of FIG. 1H, the Nxe2x88x92 doped region 110 and the N+ doped region 114 inside the island 102a, the gate 106a and the source/drain terminal 124a together constitute a polysilicon thin film transistor (poly-TFT). The writing of data into the pixel electrode 120 of the thin film transistor is driven and controlled by the CMOS.
FIG. 2 is a flow chart showing the steps for fabricating a conventional thin film transistor array and driving circuit. As shown in FIG. 2, the process of fabricating the thin film transistor array and the driving circuit includes: patterning a polysilicon layer (S200); patterning out a gate and the lower electrode of a storage capacitor (S202); patterning out a N+ doped region (S204), patterning out an Nxe2x88x92 doped region (S206); patterning out a P+ doped region (S208), patterning out a first dielectric layer (S210); patterning out source/drain terminals and the upper electrode of the storage capacitor (S212); patterning a second dielectric layer (S214) and patterning out a pixel electrode (S216).
The aforementioned method of fabricating a conventional thin film transistor array and driving circuits involves a number of masking processes such as eight (not including the fabrication of the Nxe2x88x92 doped regions 114 and 116) or nine. Since the number of masking steps required for fabricating the thin film transistor and driving circuit is high, time for producing the display panel is long and the yield is low. Hence, production cost using the conventional method is relatively high.
Accordingly, one object of the present invention is to provide a method for fabricating a thin film transistor array and driving circuit through six masking steps.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for fabricating a thin film transistor array and driving circuit. The method comprises the steps of: providing a substrate; patterning a polysilicon layer and an N+ thin film over the substrate to form a plurality of islands; patterning the islands to form P+ doped regions; patterning out source/drain terminals and the lower electrode of a storage capacitor; etching back the N+ thin film; patterning out a gate and the upper electrode of the storage capacitor and patterning a passivation layer and a conductive layer to form pixel electrodes and a wiring layout.
In this invention, after etching back the N+ thin film, an Nxe2x88x92 doped layer (lightly doped region-LDD) may form in the gap between the gate and the source/drain terminal to improve the performance of the complementary metal-oxide-semiconductor (CMOS) driving circuit consisting of a PMOS transistor and an NMOS transistor.
In this invention, the polysilicon layer is formed, for example, by depositing amorphous silicon over the substrate and conducting an excimer laser annealing (ELA) operation on the amorphous silicon layer so that the amorphous silicon layer crystallizes into a polysilicon layer.
In this invention, the N+ doped thin film is formed, for example, by directly depositing N+ doped amorphous silicon in a chemical vapor deposition process. Alternatively, the N+ doped thin film is formed, for example, by depositing amorphous silicon and then conducting an Nxe2x88x92 type ion doping process.
In this invention, the gate, the source/drain terminals and the storage capacitor are formed, for example, by first depositing conductive material to form a first conductive layer. The first conductive layer is next patterned to form a source/drain terminal on each island and a plurality of lower electrodes on the substrate. Thereafter, a second metallic layer is formed and patterned to form a gate on each island and a plurality of upper electrode on the substrate. The lower electrodes and corresponding upper electrodes together form a plurality of storage capacitors.
In an alternative method of this invention, the gate, the source/drain terminals and the storage capacitor are formed, for example, by first depositing conductive material to form a first conductive layer. The first conductive layer is next patterned to form a gate on each island and a plurality of lower electrodes on the substrate. Thereafter, a second metallic layer is formed and patterned to form a source/drain terminal on each island and a plurality of upper electrode on the substrate. The lower electrodes and corresponding upper electrodes together form a plurality of storage capacitors.
In this invention, before the step of forming the gate further includes forming a gate insulation layer. After forming the gate insulation layer, the gate insulation layer is annealed by conducting a rapid thermal processing operation.
The aforementioned gate insulation layer may include at leas a first dielectric layer, for example. The first dielectric layer is fabricated using a material such as silicon oxide, silicon nitride or hydrogen-containing dielectric material. The gate insulation layer may also comprise at least of a first dielectric layer and a second dielectric layer. The first dielectric layer is fabricated using a material such as silicon oxide, silicon nitride or hydrogen-containing dielectric material and the second dielectric layer is fabricated using a material such as photosensitive resin.
In this invention, the gate is fabricated using material such as aluminum/molybdenum or aluminum/titanium alloy and the source/drain terminal is fabricated using material such as an aluminum/molybdenum alloy or molybdenum.
For a transparent type of panel, the conductive layer can be fabricated using transparent conductive material such as indium-tin oxide. For a reflective type of panel, the conductive layer can be fabricated using a metal with good reflective properties. In addition, the surface of the passivation layer underneath the conductive layer (usually a metal with good reflective properties) may be roughed to increase light reflectivity of the conductive layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.